Multiple Power Supply Pad VDDT Testing for Delay Faults

In today's competitive IC market, success often means delivering the shortest possible clock cycle. Under pressure to push increasingly complex processing technologies to the limits, designers are delivering circuits with decreased timing and noise margins. In doing so, they are making the circuits significantly more susceptible to manufacturing imperfections. In particular, previously benign manufacturing defects can now cause circuits to fail. Manufacturing test must be able to detect these increasingly subtle defects to ensure outgoing product quality. At the same time that the IC suppliers face this increasing susceptibility to manufacturing defects, the defects themselves are becoming less and less amenable to traditional modeling and detection methods. For example, multiple metal layers increases the probability of internodal bridges over shorts to power or ground, which, in turn, reduces the chances of activation and detection under stuck-fault modeling. The likelihood of the unmodeled open defect also increases with the number of metal layers due to the larger number of vias. The " accidental " coverage of these non-stuck-at types of defects provided by functional test patterns is likely to be significantly reduced under a less aggressive structural test methodology. Reliance on such a structural test methodology is becoming unavoidable as a result of the increasingly prohibitive test generation complexity and application cost of traditional functional test. Therefore, the structural test fault model must be reformulated on alternative test metrologies in order to enable such methods to close outgoing product quality holes. A defect-based test is proposed as a means of accomplishing this goal [1]. It is defined as a procedure that (1) enumerates the likely fault sites from a mask layout representation of the device, (2) maps each " likely " defect to an appropriate fault model and (3) uses ATPG to generate tests that target these faults. Therefore, technology development of a defect-based test involves several steps including fault model development, tool development for fault extraction and simulation , model validation and ATPG. This research focuses on the fault modeling and model validation tasks. Bridging defect properties suggests that the appropriate fault model is a combination bridging (for activation) and path delay fault model (for propagation and observation). For example, the properties of the bridging fault model specify that tests must control " neighboring " off-path gate inputs for reliable activation of internodal bridges. Therefore, test generation requires physical layout information. Moreover, the resistive nature of many bridging defects require …